1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, to a floating body cell and a method for fabricating the same.
2. Description of the Related Art
A finer fabrication process of a semiconductor device confronts many technical problems, such as in the fabrication of a Dynamic Random Access Memory (DRAM), in which a unit memory cell is implemented with one transistor and one capacitor. Among these problems, it is most difficult to maintain a sufficient data retention time while improving short channel effect, and to fabricate a capacitor having sufficient capacitance while minimizing dielectric leakage in a small area. In particular, a fabrication process of a capacitor, which can ensure reliability while satisfying capacitance necessary for the operation of a DRAM, is faced with technical problems that are difficult to overcome. In an attempt to solve these problems, many experiments have been carried out on a 1T DRAM using the floating body effect of a transistor.
While a typical 1T-1C DRAM cell stores an electric charge in a capacitor, a floating body cell of the 1T DRAM is used as a memory device based on a change in threshold voltage (VT) of a transistor when an electric charge is stored. In general, a transistor forming the floating body cell is fabricated using a silicon wafer having a silicon-on-insulator (SOI) structure.
When floating body cells are fabricated using a SOI silicon wafer, adjacent cells are required to be electrically isolated from each other in order to realize two or more cells in one active region. Conventional methods involve isolating memory cells from each other using junctions by implementing high-concentration ions into sources and drains, or reducing the thickness of a silicon layer to be used as floating bodies. However, the cell isolation method using merely the junctions may degrade punch characteristics of a buried insulation layer (e.g., a buried oxide (BOX) layer) of the SOI substrate, which underlies the floating bodies. Meanwhile, the method of reducing the thickness of the floating bodies may disadvantageously reduce hole storage capability. Furthermore, the conventional cell isolation method may have a problem of data interference between adjacent cells caused by, for example, a PNP (or NPN) bipolar parasitic transistor including a p-type (or n-type) floating body, an n-type (or p-type) source/drain, and a p-type (or n-type) floating body.
The information disclosed in this Background of the Invention section is only for enhancing an understanding of the background of the invention and should not be taken as an acknowledgment or any form of suggestion that this information forms the prior art that is already known to a person skilled in the art.